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W25Q20BW publication release date: november 22, 2013 - 1 - preliminary - revision c 1.8v 2m-bit serial flash memory with dual and quad spi
W25Q20BW - 2 - table of contents 1. general description ............................... ................................................... ............................. 5 2. features .......................................... ................................................... .......................................... 5 3. pin configuration soic 150-mil and vsop 150-mil .. ................................................... ... 6 4. pad configuration wson 6x5-mm, uson 2x3-mm ........ ................................................... .. 6 5. pin description soic 150-mil, vsop, wson 6x5-mm & u son 2x3-mm ............................. 6 5.1 package types ..................................... ................................................... ............................. 7 5.2 chip select (/cs) ................................. ................................................... .............................. 7 5.3 serial data input, output and ios (di, do and io0, io1, io2, io3) .................................... . 7 5.4 write protect (/wp) ............................... ................................................... ............................ 7 5.5 hold (/hold) ...................................... ................................................... ............................ 7 5.6 serial clock (clk) ................................ ................................................... ............................. 8 6. block diagram ..................................... ................................................... .................................... 9 7. functional description ............................ ................................................... ........................ 10 7.1 spi operations .................................... ................................................... ...................... 10 7.1.1 standard spi instructions ......................... ................................................... ........................ 10 7.1.2 dual spi instructions ............................. ................................................... ............................ 10 7.1.3 quad spi instructions ............................. ................................................... .......................... 10 7.1.4 hold function ..................................... ................................................... ............................... 10 7.2 write protection .................................. ................................................... .................. 11 7.2.1 write protect features ............................ ................................................... .......................... 11 8. control and status registers ...................... ................................................... ................ 12 8.1 status register ................................... ................................................... .................... 12 8.1.1 busy .............................................. ................................................... ................................... 12 8.1.2 write enable latch (wel) .......................... ................................................... ...................... 12 8.1.3 block protect bits (bp2, bp1, bp0) ................ ................................................... .................. 12 8.1.4 top/bottom block protect (tb) ..................... ................................................... ..................... 12 8.1.5 sector/block protect (sec) ........................ ................................................... ....................... 12 8.1.6 complement protect (cmp) .......................... ................................................... .................... 13 8.1.7 status register protect (srp1, srp0) .............. ................................................... ............... 13 8.1.8 erase/program suspend status (sus) ................ ................................................... ............. 13 8.1.9 security register lock bits (lb3, lb2, lb1, lb0)... ................................................... .......... 13 8.1.10 quad enable (qe) .................................. ................................................... ......................... 14 8.1.11 status register memory protection (cmp = 0) ....... ................................................... ........ 15 8.1.12 status register memory protection (cmp = 1) ....... ................................................... ........ 16 8.2 instructions ...................................... ................................................... ........................ 17 8.2.1 manufacturer and device identification ............ ................................................... ................. 17 8.2.2 instruction set table 1 (erase, program instruction s) (1) .................................................. ..... 18
W25Q20BW publication release date: november 22, 2013 - 3 - preliminary - revision c 8.2.3 instruction set table 2 (read instructions) ....... ................................................... ................ 19 8.2.4 instruction set table 3 (id, security instructions) .................................................. .............. 20 8.2.5 write enable (06h) ................................ ................................................... ............................ 21 8.2.6 write enable for volatile status register (50h) ... ................................................... .............. 21 8.2.7 write disable (04h) ............................... ................................................... ............................ 22 8.2.8 read status register-1 (05h) and read status regist er-2 (35h) ........................................ 23 8.2.9 write status register (01h) ....................... ................................................... ........................ 23 8.2.10 read data (03h) ................................... ................................................... ........................... 25 8.2.11 fast read (0bh) ................................... ................................................... ........................... 26 8.2.12 fast read dual output (3bh) ....................... ................................................... ................... 27 8.2.13 fast read quad output (6bh) ....................... ................................................... ................. 28 8.2.14 fast read dual i/o (bbh) .......................... ................................................... ..................... 29 8.2.15 fast read quad i/o (ebh) .......................... ................................................... .................... 31 8.2.16 word read quad i/o (e7h)........................... ................................................... .................. 33 8.2.17 octal word read quad i/o (e3h) .................... ................................................... ............... 35 8.2.18 set burst with wrap (77h) ......................... ................................................... ...................... 37 8.2.19 continuous read mode bits (m7-0) .................. ................................................... .............. 38 8.2.20 continuous read mode reset (ffh or ffffh) ......... ................................................... ..... 38 8.2.21 page program (02h) ................................ ................................................... ........................ 39 8.2.22 quad input page program (32h) ..................... ................................................... ................ 40 8.2.23 sector erase (20h) ................................ ................................................... .......................... 41 8.2.24 32kb block erase (52h) ............................ ................................................... ...................... 42 8.2.25 64kb block erase (d8h) ............................ ................................................... ..................... 43 8.2.26 chip erase (c7h / 60h)............................. ................................................... ....................... 44 8.2.27 erase / program suspend (75h)...................... ................................................... ................ 45 8.2.28 erase / program resume (7ah) ...................... ................................................... ................ 46 8.2.29 power-down (b9h)................................... ................................................... ........................ 47 8.2.30 release power-down / device id (abh) .............. ................................................... ........... 48 8.2.31 read manufacturer / device id (90h) ............... ................................................... .............. 50 8.2.32 read manufacturer / device id dual i/o (92h) ...... ................................................... ......... 51 8.2.33 read manufacturer / device id quad i/o (94h) ...... ................................................... ........ 52 8.2.34 read unique id number (4bh) ....................... ................................................... ................ 53 8.2.35 read jedec id (9fh) ............................... ................................................... ...................... 54 8.2.36 erase security registers (44h) .................... ................................................... ................... 55 8.2.37 program security registers (42h) .................. ................................................... ................. 56 8.2.38 read security registers (48h) ..................... ................................................... ................... 57 9. electrical characteristics (1) .................................................. .......................................... 58 9.1 absolute maximum ratings (2) .................................................. ........................................ 58 9.2 operating ranges................................... ................................................... ......................... 58 9.3 power-up timing and write inhibit threshold ....... ................................................... .......... 59
W25Q20BW - 4 - 9.4 dc electrical characteristics ..................... ................................................... ...................... 60 9.5 ac measurement conditions ......................... ................................................... .................. 61 9.6 ac electrical characteristics ..................... ................................................... ...................... 62 9.7 ac electrical characteristics (contd) ............ ................................................... .................. 63 9.8 serial output timing .............................. ................................................... .......................... 64 9.9 serial input timing ............................... ................................................... ............................ 64 9.10 hold timing ....................................... ................................................... .............................. 64 10. package specification ............................. ................................................... .......................... 65 10.1 8-pin soic 150-mil (package code sn) .............. ................................................... ........... 65 10.2 8-pin vsop8 150-mil (package code sv) ............. ................................................... ......... 66 10.3 8-pad wson 6x5-mm (package code zp) ............... ................................................... ..... 67 10.4 8-pad uson 2x3-mm (package code ux) ............... ................................................... ..... 69 11. ordering information .............................. ................................................... ......................... 70 11.1 valid part numbers and top side marking ........... ................................................... .......... 71 12. revision history .................................. ................................................... ................................. 72
W25Q20BW publication release date: november 22, 2013 - 5 - preliminary - revision c 1. general description the W25Q20BW (2m-bit) serial flash memory provides a storage solution for systems with limited space, pins and power. the 25q series offers flexibility a nd performance well beyond ordinary serial flash devices. they are ideal for code shadowing to ram, executing code directly from dual/quad spi (xip) and storing voice, text and data. the device operat es on a single 1.65v to 1.95v power supply with current consumption as low as 4ma active and 1a fo r power-down. all devices are offered in space- saving packages. the W25Q20BW array is organized into 1,024 programm able pages of 256-bytes each. up to 256 bytes can be programmed at a time. pages can be erased in groups of 16 (4kb sector erase), groups of 128 (32kb block erase), groups of 256 (64kb block erase ) or the entire chip (chip erase). the W25Q20BW has 64 erasable sectors and 4 erasable blocks respe ctively. the small 4kb sectors allow for greater flexibility in applications that require data and p arameter storage. (see figure 2.) the W25Q20BW supports the standard serial periphera l interface (spi), and a high performance dual/quad output as well as dual/quad i/o spi: seri al clock, chip select, serial data i/o0 (di), i/o1 (do), i/o2 (/wp), and i/o3 (/hold). spi clock frequ encies of up to 80mhz are supported allowing equivalent clock rates of 160mhz (80mhz x 2) for du al i/o and 320mhz (80mhz x 4) for quad i/o when using the fast read dual/quad i/o instructions. the se transfer rates can outperform standard asynchronous 8 and 16-bit parallel flash memories. the continuous read mode allows for efficient memory access with as few as 8-clocks of instructio n-overhead to read a 24-bit address, allowing true xip (execute in place) operation. a hold pin, write protect pin and programmable writ e protection, with top, bottom or complement array control, provide further control flexibility. addit ionally, the device supports jedec standard manufac turer and device identification with a 64-bit unique seri al number. 2. features family of spiflash memories C W25Q20BW: 2m-bit/256k-byte (262,144) C 256-byte per programmable page C standard spi: clk, /cs, di, do, /wp, /hold C dual spi: clk, /cs, io 0 , io 1 , /wp, /hold C quad spi: clk, /cs, io 0 , io 1 , io 2 , io 3 highest performance serial flash C 80mhz dual/quad spi clocks C 160/320mhz equivalent dual/quad spi C 40mb/s continuous data transfer rate C up to 6x that of ordinary serial flash C more than 100,000 erase/program cycles C more than 20-year data retention efficient continuous read mode C low instruction overhead C continuous read with 8/16/32/64-byte wrap C as few as 8 clocks to address memory C allows true xip (execute in place) operation C outperforms x16 parallel flash note 1: contact winbond for details low power, wide temperature range C single 1.65 to 1.95v supply C 4ma active current, <1a power-down current C -40c to +85c operating range flexible architecture with 4kb sectors C uniform sector erase (4k-bytes) C uniform block erase (32k and 64k-bytes) C program one to 256 bytes C erase/program suspend & resume advanced security features C software and hardware write-protect C top/bottom, 4kb complement array protection C lock-down and otp array protection (1) C 64-bit unique serial number for each device C 4x256-byte security registers with otp locks C volatile & non-volatile status register bits space efficient packaging C 8-pin soic 150-mil / vsop 150-mil C 8-pad wson 6x5-mm, uson 2x3-mm C contact winbond for kgd and other options
W25Q20BW - 6 - 3. pin configuration soic 150-mil and vsop 150-mil figure 1a. W25Q20BW pin assignments, 8-pin soic 150 -mil and vsop 150-mil (package code sn & sv) 4. pad configuration wson 6x5-mm, uson 2x3-mm figure 1b. W25Q20BW pad assignments, 8-pad wson 6x5 -mm, uson 2x3-mm (package code zp & ux) 5. pin description soic 150-mil, vsop, wson 6x5-mm & uson 2x3-mm pin no. pin name i/o function 1 /cs i chip select input 2 do (io1) i/o data output (data input output 1)* 1 3 /wp (io2) i/o write protect input ( data input output 2)* 2 4 gnd ground 5 di (io0) i/o data input (data input output 0)* 1 6 clk i serial clock input 7 /hold (io3) i/o hold input (data input output 3)* 2 8 vcc power supply *1 io0 and io1 are used for standard and dual spi i nstructions *2 io0 C io3 are used for quad spi instructions
W25Q20BW publication release date: november 22, 2013 - 7 - preliminary - revision c 5.1 package types W25Q20BW is offered in an 8-pin plastic 150-mil wid th soic (package code sn), 150-mil width vsop (package code sv), 6x5-mm wson (package code zp) an d 2x3-mm uson (package code ux) as shown in figure 1a, and 1b, respectively. package d iagrams and dimensions are illustrated at the end o f this datasheet. 5.2 chip select (/cs) the spi chip select (/cs) pin enables and disables device operation. when /cs is high the device is deselected and the serial data output (do, or io0, io1, io2, io3) pins are at high impedance. when deselected, the devices power consumption will be a t standby levels unless an internal erase, program or write status register cycle is in progress. when /c s is brought low the device will be selected, power consumption will increase to active levels and inst ructions can be written to and data read from the d evice. after power-up, /cs must transition from high to low before a new instr uction will be accepted. the /cs input must track the vcc supply level at power-up ( see write protection and figure 37). if needed a pull- up resister on /cs can be used to accomplish this. 5.3 serial data input, output and ios (di, do and i o0, io1, io2, io3) the W25Q20BW supports standard spi, dual spi and qu ad spi operation. standard spi instructions use the unidirectional di (input) pin to serially w rite instructions, addresses or data to the device on the rising edge of the serial clock (clk) input pin. st andard spi also uses the unidirectional do (output) to read data or status from the device on the falling edge of clk. dual and quad spi instructions use the bidirectiona l io pins to serially write instructions, addresses or data to the device on the rising edge of clk and re ad data or status from the device on the falling ed ge of clk. quad spi instructions require the non-volat ile quad enable bit (qe) in status register-2 to be set. when qe=1, the /wp pin becomes io2 and /hold pin becomes io3. 5.4 write protect (/wp) the write protect (/wp) pin can be used to prevent the status register from being written. used in conjunction with the status registers block protec t (cmp, sec, tb, bp2, bp1 and bp0) bits and status register protect (srp) bits, a portion as small as 4kb sector or the entire memory array can be hardwa re protected. the /wp pin is active low. when the qe b it of status register-2 is set for quad i/o, the /w p pin function is not available since this pin is use d for io2. see figure 1a-c for the pin configuratio n of quad i/o operation. 5.5 hold (/hold) the /hold pin allows the device to be paused while it is actively selected. when /hold is brought low, while /cs is low, the do pin will be at high impedance and si gnals on the di and clk pins will be ignored (dont care). when /hold is brought high, device op eration can resume. the /hold function can be useful when multiple devices are sharing the same s pi signals. the /hold pin is active low. when the qe bit of status register-2 is set for quad i/o, th e /hold pin function is not available since this pi n is used for io3. see figure 1a and 1b for the pin conf iguration of quad i/o operation.
W25Q20BW - 8 - 5.6 serial clock (clk) the spi serial clock input (clk) pin provides the t iming for serial input and output operations. ("see spi operations")
W25Q20BW publication release date: november 22, 2013 - 9 - preliminary - revision c 6. block diagram figure 2. W25Q20BW serial flash memory block diagra m 00ff00h 00ffffh ? block 0 (64kb) ? 000000h 0000ffh 01ff00h 01ffffh ? block 1 (64kb) ? 010000h 0100ffh ?? ? 03ff00h 03ffffh ? block 3 (64kb) ? 030000h 0300ffh 003000h 0030ffh 002000h 0020ffh 001000h 0010ffh 000000h 0000ffh column decode and 256-byte page buffer beginning page address ending page address W25Q20BW spi command & control logic byte address latch / counter status register write control logic page address latch / counter do (io 1 ) di (io 0 ) /cs clk /hold (io 3 ) /wp (io 2 ) high voltage generators xx0f00h xx0fffh ? sector 0 (4kb) ? xx0000h xx00ffh xx1f00h xx1fffh ? sector 1 (4kb) ? xx1000h xx10ffh xx2f00h xx2fffh ? sector 2 (4kb) ? xx2000h xx20ffh ?? ? xxdf00h xxdfffh ? sector 13 (4kb) ? xxd000h xxd0ffh xxef00h xxefffh ? sector 14 (4kb) ? xxe000h xxe0ffh xxff00h xxffffh ? sector 15 (4kb) ? xxf000h xxf0ffh block segmentation data security register 3 - 0 write protect logic and row decode 00ff00h 00ffffh ? block 0 (64kb) ? 000000h 0000ffh 01ff00h 01ffffh ? block 1 (64kb) ? 010000h 0100ffh ?? ? 03ff00h 03ffffh ? block 3 (64kb) ? 030000h 0300ffh 003000h 0030ffh 002000h 0020ffh 001000h 0010ffh 000000h 0000ffh column decode and 256-byte page buffer beginning page address ending page address W25Q20BW spi command & control logic byte address latch / counter status register write control logic page address latch / counter do (io 1 ) di (io 0 ) /cs clk /hold (io 3 ) /wp (io 2 ) high voltage generators xx0f00h xx0fffh ? sector 0 (4kb) ? xx0000h xx00ffh xx1f00h xx1fffh ? sector 1 (4kb) ? xx1000h xx10ffh xx2f00h xx2fffh ? sector 2 (4kb) ? xx2000h xx20ffh ?? ? xxdf00h xxdfffh ? sector 13 (4kb) ? xxd000h xxd0ffh xxef00h xxefffh ? sector 14 (4kb) ? xxe000h xxe0ffh xxff00h xxffffh ? sector 15 (4kb) ? xxf000h xxf0ffh block segmentation data security register 3 - 0 write protect logic and row decode
W25Q20BW - 10 - 7. functional description 7.1 spi operations 7.1.1 standard spi instructions the W25Q20BW is accessed through an spi compatible bus consisting of four signals: serial clock (clk), chip select (/cs), serial data input (di) an d serial data output (do). standard spi instruction s use the di input pin to serially write instructions , addresses or data to the device on the rising edg e of clk. the do output pin is used to read data or stat us from the device on the falling edge clk. spi bus operation modes 0 (0,0) and 3 (1,1) are sup ported. the primary difference between mode 0 and mode 3 concerns the normal state of the clk signal when the spi bus master is in standby and data is not being transferred to the serial flash. for mode 0 the clk signal is normally low on the falling an d rising edges of /cs. for mode 3 the clk signal is n ormally high on the falling and rising edges of /cs . 7.1.2 dual spi instructions the W25Q20BW supports dual spi operation when using the fast read dual output (3bh) and fast read dual i/o (bbh) instructions. these instructio ns allow data to be transferred to or from the devi ce at two to three times the rate of ordinary serial flas h devices. the dual spi read instructions are ideal for quickly downloading code to ram upon power-up (code -shadowing) or for executing non-speed-critical code directly from the spi bus (xip). when using du al spi instructions, the di and do pins become bidirectional i/o pins: io0 and io1. 7.1.3 quad spi instructions the W25Q20BW supports quad spi operation when using the fast read quad output (6bh), fast read quad i/o (ebh), word read quad i/o (e7h) an d octal word read quad i/o (e3h) instructions. these instructions allow data to be transferred to or from the device six to eight times the rate of o rdinary serial flash. the quad read instructions offer a si gnificant improvement in continuous and random access transfer rates allowing fast code-shadowing to ram or execution directly from the spi bus (xip) . when using quad spi instructions the di and do pins become bidirectional io0 and io1, and the /wp and /hold pins become io2 and io3 respectively. qua d spi instructions require the non-volatile quad enable bit (qe) in status register-2 to be set. 7.1.4 hold function for standard spi and dual spi operations, the /hold signal allows the W25Q20BW operation to be paused while it is actively selected (when /cs is l ow). the /hold function may be useful in cases where the spi data and clock signals are shared with othe r devices. for example, consider if the page buffer was only partially written when a priority interrup t requires use of the spi bus. in this case the /hold function can save the state of the instruction and the data in the buffer so programming can resume where it left off once the bus is available again. the /hold function is only available for standard s pi and dual spi operation, not during quad spi. to initiate a /hold condition, the device must be selected with /cs low . a /hold condition will activate the falling edge of the /hold signal if the clk sig nal is already low. if the clk is not already low t he /hold condition will activate after the next falling edge of clk. the /hold condition will terminate on the rising edge of the /hold signal if the clk signal is already low. if the clk is not already low the /hold
W25Q20BW publication release date: november 22, 2013 - 11 - preliminary - revisio n c condition will terminate after the next falling edg e of clk. during a /hold condition, the serial data output (do) is high impedance, and serial data inpu t (di) and serial clock (clk) are ignored. the chip select (/cs) signal should be kept active low for t he full duration of the /hold operation to avoid resetting the internal logic state of the device. 7.2 write protection applications that use non-volatile memory must take into consideration the possibility of noise and ot her adverse system conditions that may compromise data integrity. to address this concern, the W25Q20BW provides several means to protect the data from ina dvertent writes. 7.2.1 write protect features device resets when vcc is below threshold time delay write disable after power-up write enable/disable instructions and automatic wr ite disable after erase or program software and hardware (/wp pin) write protection u sing status register write protection using power-down instruction lock down write protection until next power-up one time program (otp) write protection * * note: this feature is available upon special order. pleas e contact winbond for details. upon power-up or at power-down, the W25Q20BW will m aintain a reset condition while vcc is below the threshold value of v wi , (see power-up timing and voltage levels and figur e 37). while reset, all operations are disabled and no instructions are rec ognized. during power-up and after the vcc voltage exceeds v wi , all program and erase related instructions are fu rther disabled for a time delay of t puw . this includes the write enable, page program, sector era se, block erase, chip erase and the write status register instructions. note that the chip select pi n (/cs) must track the vcc supply level at power-up until the vcc-min level and t vsl time delay is reached. if needed a pull-up resiste r on /cs can be used to accomplish this. after power-up the device is automatically placed i n a write-disabled state with the status register w rite enable latch (wel) set to a 0. a write enable instr uction must be issued before a page program, sector erase, block erase, chip erase or write status regi ster instruction will be accepted. after completing a program, erase or write instruction the write enabl e latch (wel) is automatically cleared to a write- disabled state of 0. software controlled write protection is facilitated using the write status register instruction and se tting the status register protect (srp0, srp1) and block protect (cmp, sec,tb, bp2, bp1 and bp0) bits. these settings allow a portion as small as 4kb sect or or the entire memory array to be configured as read only. used in conjunction with the write prote ct (/wp) pin, changes to the status register can be enabled or disabled under hardware control. see sta tus register section for further information. additionally, the power-down instruction offers an extra level of write protection as all instructions are ignored except for the release power-down instructi on.
W25Q20BW - 12 - 8. control and status registers the read status register-1 and status register-2 in structions can be used to provide status on the availability of the flash memory array, if the devi ce is write enabled or disabled, the state of write protection, quad spi setting, security register loc k status and erase/program suspend status. the write status register instruction can be used to co nfigure the device write protection features, quad spi setting and security register otp lock. write acces s to the status register is controlled by the state of the non-volatile status register protect bits (srp0, sr p1), the write enable instruction, and during standard/dual spi operations, the /wp pin. 8.1 status register 8.1.1 busy busy is a read only bit in the status register (s0) that is set to a 1 state when the device is execut ing a page program, quad page program, sector erase, bloc k erase, chip erase, write status register or erase/program security register instruction. during this time the device will ignore further instructi ons except for the read status register and erase/progr am suspend instruction (see t w , t pp , t se , t be , and t ce in ac characteristics). when the program, erase or write status/security register instruction has completed, the busy bit will be cleared to a 0 stat e indicating the device is ready for further instru ctions. 8.1.2 write enable latch (wel) write enable latch (wel) is a read only bit in the status register (s1) that is set to 1 after executi ng a write enable instruction. the wel status bit is cle ared to 0 when the device is write disabled. a writ e disable state occurs upon power-up or after any of the following instructions: write disable, page program, quad page program, sector erase, block era se, chip erase, write status register, erase security register and program security register. 8.1.3 block protect bits (bp2, bp1, bp0) the block protect bits (bp2, bp1, bp0) are non-vola tile read/write bits in the status register (s4, s3 , and s2) that provide write protection control and statu s. block protect bits can be set using the write st atus register instruction (see t w in ac characteristics). all, none or a portion of the memory array can be protected from program and erase instructions (see status register memory protection table). the factory default setting for the block protection bi ts is 0, none of the array protected. 8.1.4 top/bottom block protect (tb) the non-volatile top/bottom bit (tb) controls if th e block protect bits (bp2, bp1, bp0) protect from t he top (tb=0) or the bottom (tb=1) of the array as sho wn in the status register memory protection table. the factory default setting is tb=0. the tb bit can be set with the write status register instruction depending on the state of the srp0, srp1 and wel bi ts. 8.1.5 sector/block protect (sec) the non-volatile sector/block protect bit (sec) con trols if the block protect bits (bp2, bp1, bp0) pro tect either 4kb sectors (sec=1) or 64kb blocks (sec=0) i n the top (tb=0) or the bottom (tb=1) of the array as shown in the status register memory protection t able. the default setting is sec=0.
W25Q20BW publication release date: november 22, 2013 - 13 - preliminary - revisio n c 8.1.6 complement protect (cmp) the complement protect bit (cmp) is a non-volatile read/write bit in the status register (s14). it is used in conjunction with sec, tb, bp2, bp1 and bp0 bits to provide more flexibility for the array protection. once cmp is set to 1, previous array protection set by s ec, tb, bp2, bp1 and bp0 will be reversed. for instance, when cmp=0, a top 4kb sector can be prote cted while the rest of the array is not; when cmp=1 , the top 4kb sector will become unprotected while th e rest of the array become read-only. please refer to the status register memory protection table for det ails. the default setting is cmp=0. 8.1.7 status register protect (srp1, srp0) the status register protect bits (srp1 and srp0) ar e non-volatile read/write bits in the status regist er (s8 and s7). the srp bits control the method of wri te protection: software protection, hardware protection, power supply lock-down or one time prog rammable (otp) protection. srp1 srp0 /wp status register description 0 0 x software protection /wp pin has no control. the status register can be written to after a write enable instruction, wel=1. [factory d efault] 0 1 0 hardware protected when /wp pin is low the status register locked and can not be written to. 0 1 1 hardware unprotected when /wp pin is high the status register is unlocke d and can be written to after a write enable instruction, wel =1. 1 0 x power supply lock-down status register is protected and can not be written to again until the next power-down, power-up cycle. (1) 1 1 x one time program (2) status register is permanently protected and can no t be written to. note: 1. when srp1, srp0 = (1, 0), a power-down, power-u p cycle will change srp1, srp0 to (0, 0) state. 2. this feature is available upon special order. pleas e contact winbond for details. 8.1.8 erase/program suspend status (sus) the suspend status bit is a read only bit in the st atus register (s15) that is set to 1 after executin g a erase/program suspend (75h) instruction. the sus st atus bit is cleared to 0 by erase/program resume (7ah) instruction as well as a power-down, power-up cycle. 8.1.9 security register lock bits (lb3, lb2, lb1, l b0) the security register lock bits (lb3, lb2, lb1, lb0 ) are non-volatile one time program (otp) bits in status register (s13, s12, s11, s10) that provide t he write protect control and status to the security registers. the default state of lb3-0 is 0, securit y registers are unlocked. lb3-0 can be set to 1 individually using the write status register instru ction. lb3-0 are one time programmable (otp), once its set to 1, the corresponding 256-byte security register will become read-only permanently.
W25Q20BW - 14 - 8.1.10 quad enable (qe) the quad enable (qe) bit is a non-volatile read/wri te bit in the status register (s9) that allows quad spi operation. when the qe bit is set to a 0 state (fac tory default), the /wp pin and /hold are enabled. when the qe bit is set to a 1, the quad io2 and io3 pins are enabled. warning: the qe bit should never be set to a 1 duri ng standard spi or dual spi operation if the /wp or /hold pins are tied directly to the power su pply or ground. s7 s6 s5 s4 s3 s2 s1 s0 srp0 sec tb bp2 bp1 bp0 wel busy status register protect 0 (non-volatile) sector protect (non-volatile) top/bottom protect (non-volatile) block protect bits (non-volatile) write enable latch erase/write in progress s7 s6 s5 s4 s3 s2 s1 s0 srp0 sec tb bp2 bp1 bp0 wel busy status register protect 0 (non-volatile) sector protect (non-volatile) top/bottom protect (non-volatile) block protect bits (non-volatile) write enable latch erase/write in progress figure 3a. status register-1 s15 s14 s13 s12 s11 s10 s9 s8 sus cmp lb3 lb2 lb1 lb0 qe srp1 suspend status complement protect (non-volatile) security register lock bits (non-volatile otp) quad enable (non-volatile) status register protect 1 (non - volatile) s15 s14 s13 s12 s11 s10 s9 s8 sus cmp lb3 lb2 lb1 lb0 qe srp1 suspend status complement protect (non-volatile) security register lock bits (non-volatile otp) quad enable (non-volatile) status register protect 1 (non - volatile) figure 3b. status register-2
W25Q20BW publication release date: november 22, 2013 - 15 - preliminary - revisio n c 8.1.11 status register memory protection (cmp = 0) status register (1) W25Q20BW 2m-bit memory protected (2) sec tb bp2 bp1 bp0 block(s) addresses density portion 0 x x 0 0 none none none none 0 0 x 0 1 3 030000h C 03ffffh 64kb upper 1/4 0 0 x 1 0 2 and 3 020000h C 03ffffh 128kb upper 1/2 0 1 x 0 1 0 000000h C 00ffffh 64kb lower 1/4 0 1 x 1 0 0 and 1 000000h C 01ffffh 128kb lower 1/2 0 x x 1 1 0 thru 3 000000h C 03ffffh 256kb all 1 x 0 0 0 none none none none 1 0 0 0 1 3 03f000h C 03ffffh 4kb upper 1/64 1 0 0 1 0 3 03e000h C 03ffffh 8kb upper 1/32 1 0 0 1 1 3 03c000h C 03ffffh 16kb upper 1/16 1 0 1 0 x 3 038000h C 03ffffh 32kb upper 1/8 1 1 0 0 1 0 000000h C 000fffh 4kb lower 1/64 1 1 0 1 0 0 000000h C 001fffh 8kb lower 1/32 1 1 0 1 1 0 000000h C 003fffh 16kb lower 1/16 1 1 1 0 x 0 000000h C 007fffh 32kb lower 1/8 1 x 1 1 1 0 thru 3 000000h C 03ffffh 256kb all notes: 1. x = dont care 2. if any erase or program command specifies a memo ry region that contains protected data portion, thi s command will be ignored.
W25Q20BW - 16 - 8.1.12 status register memory protection (cmp = 1) status register (1) W25Q20BW 2m-bit memory protected (2) sec tb bp2 bp1 bp0 block(s) addresses density portion 0 x x 0 0 0 thru 3 000000h C 03ffffh 256kb all 0 0 x 0 1 0 thru 2 000000h C 02ffffh 192kb lower 3/ 4 0 0 x 1 0 0 and 1 000000h C 01ffffh 128kb lower 1/2 0 1 x 0 1 1 thru 3 010000h C 03ffffh 192kb upper 3/ 4 0 1 x 1 0 2 and 3 020000h C 03ffffh 128kb upper 1/2 0 x x 1 1 none none none none 1 x 0 0 0 0 thru 3 000000h C 03ffffh 256kb all 1 0 0 0 1 0 thru 3 000000h C 03efffh 252kb lower 63 /64 1 0 0 1 0 0 thru 3 000000h C 03dfffh 248kb lower 31 /32 1 0 0 1 1 0 thru 3 000000h C 03bfffh 240kb lower 15/16 1 0 1 0 x 0 thru 3 000000h C 037fffh 224kb lower 7/ 8 1 1 0 0 1 0 thru 3 001000h C 03ffffh 252kb upper 63 /64 1 1 0 1 0 0 thru 3 002000h C 03ffffh 248kb upper 31 /32 1 1 0 1 1 0 thru 3 004000h C 03ffffh 240kb upper 15 /16 1 1 1 0 x 0 thru 3 008000h C 03ffffh 224kb upper 7/ 8 1 x 1 1 1 none none none none notes: 1. x = dont care 2. if any erase or program command specifies a memo ry region that contains protected data portion, thi s command will be ignored.
W25Q20BW publication release date: november 22, 2013 - 17 - preliminary - revisio n c 8.2 instructions the instruction set of the W25Q20BW consists of thi rty four basic instructions that are fully controll ed through the spi bus (see instruction set table1-3). instructions are initiated with the falling edge o f chip select (/cs). the first byte of data clocked into t he di input provides the instruction code. data on the di input is sampled on the rising edge of clock with m ost significant bit (msb) first. instructions vary in length from a single byte to s everal bytes and may be followed by address bytes, data bytes, dummy bytes (dont care), and in some cases, a combination. instructions are completed with the rising edge of edge /cs. clock relative timing diag rams for each instruction are included in figures 4 through 36. all read instructions can be completed after any clocked bit. however, all instructions th at write, program or erase must complete on a byte bou ndary (/cs driven high after a full 8-bits have bee n clocked) otherwise the instruction will be ignored. this feature further protects the device from inad vertent writes. additionally, while the memory is being pro grammed or erased, or when the status register is being written, all instructions except for read sta tus register will be ignored until the program or e rase cycle has completed. 8.2.1 manufacturer and device identification manufacturer id (mf7-mf0) winbond serial flash efh device id (id7-id0) (id15-id0) instruction abh, 90h, 92h, 94h 9fh W25Q20BW 11h 5012h
W25Q20BW - 18 - 8.2.2 instruction set table 1 (erase, program instr uctions) (1) instruction name byte 1 (code) byte 2 byte 3 byte 4 byte 5 byte 6 write enable 06h write enable for volatile status register 50h write disable 04h read status register-1 05h (s7Cs0) (2) read status register-2 35h (s15Cs8) (2) write status register 01h s7Cs0 s15-s8 page program 02h a23Ca16 a15Ca8 a7Ca0 d7Cd0 quad page program 32h a23Ca16 a15Ca8 a7Ca0 d7Cd0, (3) sector erase (4kb) 20h a23Ca16 a15Ca8 a7Ca0 block erase (32kb) 52h a23Ca16 a15Ca8 a7Ca0 block erase (64kb) d8h a23Ca16 a15Ca8 a7Ca0 chip erase c7h/60h erase / program suspend 75h erase / program resume 7ah power-down b9h continuous read mode reset (4) ffh ffh notes: 1. data bytes are shifted with most significant bit first. byte fields with data in parenthesis () i ndicate data being read from the device on the do pin. 2. the status register contents will repeat continu ously until /cs terminates the instruction. 3. quad page program input data: io0 = d4, d0, io1 = d5, d1, io2 = d6, d2, io3 = d7, d3, 4. this instruction is recommended when using the d ual or quad continuous read mode feature. see sec tion 8.2.19 & 8.2.20 for more information.
W25Q20BW publication release date: november 22, 2013 - 19 - preliminary - revisio n c 8.2.3 instruction set table 2 (read instructions) instruction name byte 1 (code) byte 2 byte 3 byte 4 byte 5 byte 6 read data 03h a23-a16 a15-a8 a7-a0 (d7-d0) fast read 0bh a23-a16 a15-a8 a7-a0 dummy (d7-d0) fast read dual output 3bh a23-a16 a15-a8 a7-a0 dummy (d7-d0, ) (1) fast read quad output 6bh a23-a16 a15-a8 a7-a0 dummy (d7-d0, ) (3) fast read dual i/o bbh a23-a8 (2) a7-a0, m7-m0 (2) (d7-d0, ) (1) fast read quad i/o ebh a23-a0, m7-m0 (4) (x,x,x,x, d7-d0,) (5) (d7-d0, ) (3) word read quad i/o (7) e7h a23-a0, m7-m0 (4) (x,x, d7-d0, ) (6) (d7-d0, ) (3) octal word read quad i/o (8) e3h a23-a0, m7-m0 (4) (d7-d0, ) (3) set burst with wrap 77h xxxxxx, w6-w4 (4) notes: 1. dual output data io0 = (d6, d4, d2, d0) io1 = (d7, d5, d3, d1) 2. dual input address io0 = a22, a20, a18, a16, a14, a12, a10, a8 a6, a4 , a2, a0, m6, m4, m2, m0 io1 = a23, a21, a19, a17, a15, a13, a11, a9 a7, a5 , a3, a1, m7, m5, m3, m1 3. quad output data io0 = (d4, d0, ..) io1 = (d5, d1, ..) io2 = (d6, d2, ..) io3 = (d7, d3, ..) 4. quad input address set burst with wrap input io0 = a20, a16, a12, a8, a4, a0, m4, m0 io0 = x, x, x, x, x, x, w4, x io1 = a21, a17, a13, a9, a5, a1, m5, m1 io1 = x, x, x, x, x, x, w5, x io2 = a22, a18, a14, a10, a6, a2, m6, m2 io2 = x, x, x, x, x, x, w6, x io3 = a23, a19, a15, a11, a7, a3, m7, m3 io3 = x, x, x, x, x, x, x, x 5. fast read quad i/o data io0 = (x, x, x, x, d4, d0, ..) io1 = (x, x, x, x, d5, d1, ..) io2 = (x, x, x, x, d6, d2, ..) io3 = (x, x, x, x, d7, d3, ..) 6. word read quad i/o data io0 = (x, x, d4, d0, ..) io1 = (x, x, d5, d1, ..) io2 = (x, x, d6, d2, ..) io3 = (x, x, d7, d3, ..) 7. the lowest address bit must be 0. ( a0 = 0 ) 8. the lowest 4 address bits must be 0. ( a0, a1, a 2, a3 = 0 )
W25Q20BW - 20 - 8.2.4 instruction set table 3 (id, security instruc tions) instruction name byte 1 (code) byte 2 byte 3 byte 4 byte 5 byte 6 release power down/ device id abh dummy dummy dummy (id7-id0) (1) manufacturer/ device id (2) 90h dummy dummy 00h (mf7-mf0) (id7-id0) manufacturer/device id by dual i/o 92h a23-a8 a7-a0, m[7:0] (mf[7:0], id[7:0]) manufacture/device id by quad i/o 94h a23-a0, m[7:0] xxxx, (mf[7:0], id[7:0]) (mf[7:0], id[7:0], ) jedec id 9fh (mf7-mf0) manufacturer (id15-id8) memory type (id7-id0) capacity read unique id 4bh dummy dummy dummy dummy (id63-id0) erase security registers (3) 44h a23Ca16 a15Ca8 a7Ca0 program security registers (3) 42h a23Ca16 a15Ca8 a7Ca0 d7-d0 d7-d0 read security registers (3) 48h a23Ca16 a15Ca8 a7Ca0 dummy (d7-0) notes: 1. the device id will repeat continuously until /cs terminates the instruction. 2. see manufacturer and device identification table for device id information. 3. security register address: security register 0: a23-16 = 00h; a15-8 = 00h; a7-0 = byte address security register 1: a23-16 = 00h; a15-8 = 10h; a7-0 = byte address security register 2: a23-16 = 00h; a15-8 = 20h; a7-0 = byte address security register 3: a23-16 = 00h; a15-8 = 30h; a7-0 = byte address please note that security register 0 is reserved by winbond for future use. it is recommended to use s ecurity registers 1- 3 before using register 0.
W25Q20BW publication release date: november 22, 2013 - 21 - preliminary - revisio n c 8.2.5 write enable (06h) the write enable instruction (figure 4) sets the wr ite enable latch (wel) bit in the status register t o a 1. the wel bit must be set prior to every page prog ram, quad page program, sector erase, block erase, chip erase, write status register and erase/ program security registers instruction. the write enable instruction is entered by driving /cs low, s hifting the instruction code 06h into the data in put (di) pin on the rising edge of clk, and then driving /cs high. figure 4. write enable instruction sequence diagram 8.2.6 write enable for volatile status register (50 h) the non-volatile status register bits described in section 8.1 can also be written to as volatile bits . this gives more flexibility to change the system configu ration and memory protection schemes quickly withou t waiting for the typical non-volatile bit write cycl es or affecting the endurance of the status registe r non- volatile bits. to write the volatile values into th e status register bits, the write enable for volati le status register (50h) instruction must be issued prior to a write status register (01h) instruction. write en able for volatile status register instruction (figure 5) will not set the write enable latch (wel) bit, it is only valid for the write status register instruction to change the volatile status register bit values. figure 5. write enable for volatile status register instruction sequence diagram instruction (50h)
W25Q20BW - 22 - 8.2.7 write disable (04h) the write disable instruction (figure 6) resets the write enable latch (wel) bit in the status registe r to a 0. the write disable instruction is entered by dr iving /cs low, shifting the instruction code 04h into the di pin and then driving /cs high. note that the wel bit is automatically reset after power-up and upon completion of the write status register, erase/prog ram security registers, page program, quad page program, sector erase, block erase and chip erase i nstructions. write disable instruction can also be used to inval idate the write enable for volatile status register instruction. figure 6. write disable instruction sequence diagra m
W25Q20BW publication release date: november 22, 2013 - 23 - preliminary - revisio n c 8.2.8 read status register-1 (05h) and read status register-2 (35h) the read status register instructions allow the 8-b it status registers to be read. the instruction is entered by driving /cs low and shifting the instruc tion code 05h for status register-1 or 35h for status register-2 into the di pin on the rising edg e of clk. the status register bits are then shifted out on the do pin at the falling edge of clk with most sig nificant bit (msb) first as shown in figure 7. the status register bits are shown in figure 3a and 3b and inc lude the busy, wel, bp2-bp0, tb, sec, srp0, srp1, qe, lb3-0, cmp and sus bits (see status regis ter section earlier in this datasheet). the read status register instruction may be used at any time, even while a program, erase or write status register cycle is in progress. this allows t he busy status bit to be checked to determine when the cycle is complete and if the device can accept another instruction. the status register can be rea d continuously, as shown in figure 7. the instruction is completed by driving /cs high. figure 7. read status register instruction sequence diagram 8.2.9 write status register (01h) the write status register instruction allows the st atus register to be written. only non-volatile stat us register bits srp0, sec, tb, bp2, bp1, bp0 (bits 7 thru 2 of status register-1) and cmp, lb3, lb2, lb1, lb0, qe, srp1 (bits 14 thru 8 of status regist er-2) can be written to. all other status register bit locations are read-only and will not be affected by the write status register instruction. lb3-0 are n on- volatile otp bits, once it is set to 1, it can not be cleared to 0. the status register bits are shown in figure 3 and described in 10.1. to write non-volatile status register bits, a stand ard write enable (06h) instruction must previously have been executed for the device to accept the write st atus register instruction (status register bit wel must equal 1). once write enabled, the instruction is entered by driving /cs low, sending the instruct ion code 01h, and then writing the status register da ta byte as illustrated in figure 8. to write volatile status register bits, a write ena ble for volatile status register (50h) instruction must have been executed prior to the write status regist er instruction (status register bit wel remains 0). however, srp1 and lb3, lb2, lb1, lb0 can not be cha nged from 1 to 0 because of the otp protection for these bits. upon power off, the vola tile status register bit values will be lost, and t he non- volatile status register bit values will be restore d when power on again.
W25Q20BW - 24 - to complete the write status register instruction, the /cs pin must be driven high after the eighth or sixteenth bit of data that is clocked in. if this i s not done the write status register instruction wi ll not be executed. if /cs is driven high after the eighth cl ock (compatible with the 25x series) the cmp, qe an d srp1 bits will be cleared to 0. during non-volatile status register write operation (06h combined with 01h), after /cs is driven high, the self-timed write status register cycle will commenc e for a time duration of t w (see ac characteristics). while the write status register cycle is in progres s, the read status register instruction may still b e accessed to check the status of the busy bit. the b usy bit is a 1 during the write status register cyc le and a 0 when the cycle is finished and ready to acc ept other instructions again. after the write statu s register cycle has finished, the write enable latch (wel) bit in the status register will be cleared t o 0. during volatile status register write operation (50 h combined with 01h), after /cs is driven high, the status register bits will be refreshed to the new v alues within the time period of t shsl2 (see ac characteristics). busy bit will remain 0 during the status register bit refresh period. please refer to 10.1 for detailed status register b it descriptions. factory default for all status reg ister bits are 0. 15 14 13 12 11 10 9 8 status register 1 status register 2 15 14 13 12 11 10 9 8 status register 1 status register 2 status register 2 figure 8. write status register instruction sequenc e diagram
W25Q20BW publication release date: november 22, 2013 - 25 - preliminary - revisio n c 8.2.10 read data (03h) the read data instruction allows one or more data b ytes to be sequentially read from the memory. the instruction is initiated by driving the /cs pin low and then shifting the instruction code 03h foll owed by a 24-bit address (a23-a0) into the di pin. the code a nd address bits are latched on the rising edge of t he clk pin. after the address is received, the data by te of the addressed memory location will be shifted out on the do pin at the falling edge of clk with most significant bit (msb) first. the address is automat ically incremented to the next higher address after each b yte of data is shifted out allowing for a continuou s stream of data. this means that the entire memory c an be accessed with a single instruction as long as the clock continues. the instruction is completed b y driving /cs high. the read data instruction sequence is shown in figu re 9. if a read data instruction is issued while an erase, program or write cycle is in process (busy=1 ) the instruction is ignored and will not have any effects on the current cycle. the read data instruc tion allows clock rates from d.c. to a maximum of f r (see ac electrical characteristics). figure 9. read data instruction sequence diagram
W25Q20BW - 26 - 8.2.11 fast read (0bh) the fast read instruction is similar to the read da ta instruction except that it can operate at the hi ghest possible frequency of f r (see ac electrical characteristics). this is accom plished by adding eight dummy clocks after the 24-bit address as shown in figure 10. the dummy clocks allow the devices internal circuits additional time for setting up th e initial address. during the dummy clocks the data value on the do pin is a dont care. figure 10. fast read instruction sequence diagram
W25Q20BW publication release date: november 22, 2013 - 27 - preliminary - revisio n c 8.2.12 fast read dual output (3bh) the fast read dual output (3bh) instruction is simi lar to the standard fast read (0bh) instruction exc ept that data is output on two pins; io 0 and io 1 . this allows data to be transferred from the w25q2 0bw at twice the rate of standard spi devices. the fast re ad dual output instruction is ideal for quickly downloading code from flash to ram upon power-up or for applications that cache code-segments to ram for execution. similar to the fast read instruction, the fast read dual output instruction can operate at the highest possible frequency of f r (see ac electrical characteristics). this is accom plished by adding eight dummy clocks after the 24-bit address as shown in figure 11. the dummy clocks allow the device's internal circuits additional time for setting up th e initial address. the input data during the dummy clocks is dont care. however, the io 0 pin should be high-impedance prior to the falling edge of the first data out clock. figure 11. fast read dual output instruction sequen ce diagram
W25Q20BW - 28 - 8.2.13 fast read quad output (6bh) the fast read quad output (6bh) instruction is simi lar to the fast read dual output (3bh) instruction except that data is output on four pins, io 0 , io 1 , io 2 , and io 3 . a quad enable of status register-2 must be executed before the device will accept the fast read quad output instruction (status register bit q e must equal 1). the fast read quad output instructio n allows data to be transferred from the W25Q20BW at four times the rate of standard spi dev ices. the fast read quad output instruction can operate a t the highest possible frequency of f r (see ac electrical characteristics). this is accomplished b y adding eight dummy clocks after the 24-bit addr ess as shown in figure 12. the dummy clocks allow the d evice's internal circuits additional time for setti ng up the initial address. the input data during the dumm y clocks is dont care. however, the io pins shou ld be high-impedance prior to the falling edge of the first data out clock. figure 12. fast read quad output instruction sequen ce diagram
W25Q20BW publication release date: november 22, 2013 - 29 - preliminary - revisio n c 8.2.14 fast read dual i/o (bbh) the fast read dual i/o (bbh) instruction allows for improved random access while maintaining two io pins, io 0 and io 1 . it is similar to the fast read dual output (3bh) instruction but with the capability to input the address bits (a23-0) two bits per clock. this r educed instruction overhead may allow for code execution (xip) directly from the dual spi in some applications. fast read dual i/o with continuous read mode the fast read dual i/o instruction can further redu ce instruction overhead through setting the continuous read mode bits (m7-0) after the input address bits (a23-0), as shown in figure 13a. the upper nibble of the (m7-4) controls the length of t he next fast read dual i/o instruction through the inclusion or exclusion of the first byte instructio n code. the lower nibble bits of the (m3-0) are don t care (x). however, the io pins should be high-impedanc e prior to the falling edge of the first data out c lock. if the continuous read mode bits m5-4 = (1,0), th en the next fast read dual i/o instruction (after / cs is raised and then lowered) does not require the bbh i nstruction code, as shown in figure 13b. this reduc es the instruction sequence by eight clocks and allows the read address to be immediately entered after / cs is asserted low. if the continuous read mode bits m5-4 do not equal to (1,0), the next instruction ( after /cs is raised and then lowered) requires the first byte instruction code, thus returning to normal ope ration. a continuous read mode reset instruction can also be used to reset (m7-0) before issuing normal instructions (see 8.2.20 for detail descriptions). figure 13a. fast read dual i/o instruction sequence (initial instruction or previous m5-4 1 10)
W25Q20BW - 30 - figure 13b. fast read dual i/o instruction sequence (previous instruction set m5-4 = 10)
W25Q20BW publication release date: november 22, 2013 - 31 - preliminary - revisio n c 8.2.15 fast read quad i/o (ebh) the fast read quad i/o (ebh) instruction is similar to the fast read dual i/o (bbh) instruction except that address and data bits are input and output thr ough four pins io 0 , io 1 , io 2 and io 3 and four dummy clock are required prior to the data output . the quad i/o dramatically reduces instruction over head allowing faster random access for code execution (x ip) directly from the quad spi. the quad enable bit (qe) of status register-2 must be set to enable the fast read quad i/o instruction. fast read quad i/o with continuous read mode the fast read quad i/o instruction can further redu ce instruction overhead through setting the continuous read mode bits (m7-0) after the input address bits (a23-0), as shown in figure 14a. the upper nibble of the (m7-4) controls the length of t he next fast read quad i/o instruction through the inclusion or exclusion of the first byte instructio n code. the lower nibble bits of the (m3-0) are don t care (x). however, the io pins should be high-impedanc e prior to the falling edge of the first data out c lock. if the continuous read mode bits m5-4 = (1,0), th en the next fast read quad i/o instruction (after / cs is raised and then lowered) does not require the eb h instruction code, as shown in figure 14b. this reduces the instruction sequence by eight clocks an d allows the read address to be immediately entered after /cs is asserted low. if the continuous read mode bits m5-4 do not equal to (1,0), the next instruction (after /cs is raised and then lowered) requires the first byte instruction code, thus retu rning to normal operation. a continuous read mode reset in struction can also be used to reset (m7-0) before issuing normal instructions (see 8.2.20 for detail descriptions). figure 14a. fast read quad i/o instruction sequence (initial instruction or previous m5-4 1 10) byte 1 byte 2 byte 1 byte 2
W25Q20BW - 32 - figure 14b. fast read quad i/o instruction sequence (previous instruction set m5-4 = 10) fast read quad i/o with 8/16/32/64-byte wrap aroun d the fast read quad i/o instruction can also be used to access a specific portion within a page by issu ing a set burst with wrap command prior to ebh. the set burst with wrap command can either enable or disable the wrap around feature for the following ebh commands. when wrap around is enabled, the data being accessed can be limited to either a 8, 1 6, 32 or 64-byte section of a 256-byte page. the ou tput data starts at the initial address specified in the instruction, once it reaches the ending boundary o f the 8/16/32/64-byte section, the output will wrap aroun d to the beginning boundary automatically until /cs is pulled high to terminate the command. the burst with wrap feature allows applications tha t use cache to quickly fetch a critical address and then fill the cache afterwards within a fixed length (8/ 16/32/64-byte) of data without issuing multiple rea d commands. the set burst with wrap instruction allows three wrap bits, w6-4 to be set. the w4 bit is used to enable or disable the wrap around operation while w6-5 are used to specify the length of the wrap around section within a page. see 8.2.18 for detail descriptions.
W25Q20BW publication release date: november 22, 2013 - 33 - preliminary - revisio n c 8.2.16 word read quad i/o (e7h) the word read quad i/o (e7h) instruction is similar to the fast read quad i/o (ebh) instruction except that the lowest address bit (a0) must equal 0 and o nly two dummy clock are required prior to the data output. the quad i/o dramatically reduces instructi on overhead allowing faster random access for code execution (xip) directly from the quad spi. the qua d enable bit (qe) of status register-2 must be set to enable the word read quad i/o instruction. word read quad i/o with continuous read mode the word read quad i/o instruction can further redu ce instruction overhead through setting the continuous read mode bits (m7-0) after the input address bits (a23-0), as shown in figure 15a. the upper nibble of the (m7-4) controls the length of t he next fast read quad i/o instruction through the inclusion or exclusion of the first byte instructio n code. the lower nibble bits of the (m3-0) are don t care (x). however, the io pins should be high-impedanc e prior to the falling edge of the first data out c lock. if the continuous read mode bits m5-4 = (1,0), th en the next fast read quad i/o instruction (after / cs is raised and then lowered) does not require the e7 h instruction code, as shown in figure 15b. this reduces the instruction sequence by eight clocks an d allows the read address to be immediately entered after /cs is asserted low. if the continuous read mode bits m5-4 do not equal to (1,0), the next instruction (after /cs is raised and then lowered) requires the first byte instruction code, thus retu rning to normal operation. a continuous read mode reset in struction can also be used to reset (m7-0) before issuing normal instructions (see 8.2.20 for detail descriptions). figure 15a. word read quad i/o instruction sequence (initial instruction or previous m5-4 1 10) instruction (e7h) byte 1 byte 2 byte 3 4 0 4 0 4 0 5 1 5 1 5 1 6 2 6 2 6 2 7 3 7 3 7 3 instruction (e7h) byte 1 byte 2 byte 3 4 0 4 0 4 0 4 0 4 0 4 0 5 1 5 1 5 1 5 1 5 1 5 1 6 2 6 2 6 2 6 2 6 2 6 2 7 3 7 3 7 3 7 3 7 3 7 3
W25Q20BW - 34 - figure 15b. word read quad i/o instruction sequence (previous instruction set m5-4 = 10) word read quad i/o with 8/16/32/64-byte wrap aroun d the word read quad i/o instruction can also be used to access a specific portion within a page by issuing a set burst with wrap command prior to e7 h. the set burst with wrap command can either enable or disable the wrap around feature for the following e7h commands. when wrap around is enabled, the data being accessed can be limited to either a 8, 16, 32 or 64-byte section of a 256-byte page. the output data starts at the initial address specified in the instruction, once it reaches the ending boundary of the 8/16/32/64-byte section, the output will wrap around to the beginning boundary automatically until /cs is pulled high to terminate the command. the burst with wrap feature allows applications tha t use cache to quickly fetch a critical address and then fill the cache afterwards within a fixed length (8/ 16/32/64-byte) of data without issuing multiple rea d commands. the set burst with wrap instruction allows three wrap bits, w6-4 to be set. the w4 bit is used to enable or disable the wrap around operation while w6-5 are used to specify the length of the wrap around section within a page. see 8.2.18 for detail descriptions. byte 1 byte 2 byte 3 4 0 4 0 4 0 5 1 5 1 5 1 6 2 6 2 6 2 7 3 7 3 7 3 byte 1 byte 2 byte 3 4 0 4 0 4 0 4 0 4 0 4 0 5 1 5 1 5 1 5 1 5 1 5 1 6 2 6 2 6 2 6 2 6 2 6 2 7 3 7 3 7 3 7 3 7 3 7 3
W25Q20BW publication release date: november 22, 2013 - 35 - preliminary - revisio n c 8.2.17 octal word read quad i/o (e3h) the octal word read quad i/o (e3h) instruction is s imilar to the fast read quad i/o (ebh) instruction except that the lower four address bits (a0, a1, a2 , a3) must equal 0. as a result, the dummy clocks a re not required, which further reduces the instruction overhead allowing even faster random access for co de execution (xip). the quad enable bit (qe) of status register-2 must be set to enable the octal word read quad i/o instruction. octal word read quad i/o with continuous read mode the octal word read quad i/o instruction can furthe r reduce instruction overhead through setting the continuous read mode bits (m7-0) after the input address bits (a23-0), as shown in figure 16a. the upper nibble of the (m7-4) controls the length of t he next octal word read quad i/o instruction throug h the inclusion or exclusion of the first byte instru ction code. the lower nibble bits of the (m3-0) are dont care (x). however, the io pins should be high-imp edance prior to the falling edge of the first data out clock. if the continuous read mode bits m5-4 = (1,0), th en the next fast read quad i/o instruction (after / cs is raised and then lowered) does not require the e3 h instruction code, as shown in figure 16b. this reduces the instruction sequence by eight clocks an d allows the read address to be immediately entered after /cs is asserted low. if the continuous read mode bits m5-4 do not equal to (1,0), the next instruction (after /cs is raised and then lowered) requires the first byte instruction code, thus retu rning to normal operation. a continuous read mode reset in struction can also be used to reset (m7-0) before issuing normal instructions (see 8.2.20 for detail descriptions). figure 16a. octal word read quad i/o instruction se quence (initial instruction or previous m5-4 1 10) instruction (e3h) byte 1 byte 2 byte 3 4 0 4 0 4 0 5 1 5 1 5 1 6 2 6 2 6 2 7 3 7 3 7 3 4 0 5 1 6 2 7 3 byte 4 instruction (e3h) byte 1 byte 2 byte 3 4 0 4 0 4 0 4 0 4 0 4 0 5 1 5 1 5 1 5 1 5 1 5 1 6 2 6 2 6 2 6 2 6 2 6 2 7 3 7 3 7 3 7 3 7 3 7 3 4 0 4 0 5 1 5 1 6 2 6 2 7 3 7 3 byte 4
W25Q20BW - 36 - figure 16b. octal word read quad i/o instruction se quence (previous instruction set m5-4 = 10) byte 2 byte 3 byte 4 4 0 4 0 4 0 5 1 5 1 5 1 6 2 6 2 6 2 7 3 7 3 7 3 byte 1 4 0 5 1 6 2 7 3 byte 2 byte 3 byte 4 4 0 4 0 4 0 4 0 4 0 4 0 5 1 5 1 5 1 5 1 5 1 5 1 6 2 6 2 6 2 6 2 6 2 6 2 7 3 7 3 7 3 7 3 7 3 7 3 byte 1 4 0 4 0 5 1 5 1 6 2 6 2 7 3 7 3
W25Q20BW publication release date: november 22, 2013 - 37 - preliminary - revisio n c 8.2.18 set burst with wrap (77h) the set burst with wrap (77h) instruction is used i n conjunction with fast read quad i/o and word read quad i/o instructions to access a fixed lengt h of 8/16/32/64-byte section within a 256-byte page . certain applications can benefit from this feature and improve the overall system code execution performance. similar to a quad i/o instruction, the set burst wi th wrap instruction is initiated by driving the /cs pin low and then shifting the instruction code 77h follow ed by 24 dummy bits and 8 wrap bits, w7-0. the instruction sequence is shown in figure 17. wrap bi t w7 and the lower nibble w3-0 are not used. w6, w5 w4 = 0 w4 =1 (default) wrap around wrap length wrap around wrap length 0 0 yes 8-byte no n/a 0 1 yes 16-byte no n/a 1 0 yes 32-byte no n/a 1 1 yes 64-byte no n/a once w6-4 is set by a set burst with wrap instructi on, all the following fast read quad i/o and wor d read quad i/o instructions will use the w6-4 setti ng to access the 8/16/32/64-byte section within any page. to exit the wrap around function and return to normal read operation, another set burst with wrap instruction should be issued to set w4 = 1. th e default value of w4 upon power on is 1. in the ca se of a system reset while w4 = 0, it is recommended t hat the controller issues a set burst with wrap instruction to reset w4 = 1 prior to any normal rea d instructions since W25Q20BW does not have a hardware reset pin. figure 17. set burst with wrap instruction sequence 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 mode 3 mode 0 /cs clk io 0 io 1 io 2 io 3 instruction ( 77h ) dont care dont care dont care wrap bit x x x x x x x x x x x x x x x x x x x x x x x x x w6 w5 w4 x x x x 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 mode 3 mode 0 /cs clk io 0 io 1 io 2 io 3 instruction ( 77h ) dont care dont care dont care wrap bit x x x x x x x x x x x x x x x x x x x x x x x x x w6 w5 w4 x x x x x x x x x x x x x x x x x x x x x x x x x x x x x w6 w5 w4 x x x x
W25Q20BW - 38 - 8.2.19 continuous read mode bits (m7-0) the continuous read mode bits are used in conjunc tion with fast read dual i/o, fast read quad i/o, word read quad i/o and octal word read qua d i/o instructions to provide the highest random flash memory access rate with minimum spi instructi on overhead, thus allow true xip (execute in place) to be performed on serial flash devices. m7-0 need to be set by the dual/quad i/o read instr uctions. m5-4 are used to control whether the 8-bit spi instruction code (bbh, ebh, e7h or e3h) is need ed or not for the next command. when m5-4 = (1,0), the next command will be treated same as the curren t dual/quad i/o read command without needing the 8-bit instruction code; when m5-4 do not equal to ( 1,0), the device returns to normal spi mode, all commands can be accepted. m7-6 and m3-0 are reserve d bits for future use, either 0 or 1 values can be used. 8.2.20 continuous read mode reset (ffh or ffffh) continuous read mode reset instruction can be used to set m4 = 1, thus the device will release the continuous read mode and return to normal spi opera tion, as shown in figure 18. /cs mode bit reset for dual i/o mode 3 mode 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 mode 3 mode 0 mode bit reset for quad i/o ffh ffh dont care dont care dont care clk io 0 io 1 io 2 io 3 /cs mode bit reset for dual i/o mode 3 mode 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 mode 3 mode 0 mode bit reset for quad i/o ffh ffh dont care dont care dont care clk io 0 io 1 io 2 io 3 figure 18. continuous read mode reset for fast read dual/quad i/o since W25Q20BW does not have a hardware reset pin, so if the controller resets while W25Q20BW is set to continuous mode read, the W25Q20BW will not recognize any initial standard spi instructions from the controller. to address this possibility, i t is recommended to issue a continuous read mode reset instruction as the first instruction after a system reset. doing so will release the device from the continuous read mode and allow standard spi instruc tions to be recognized. to reset continuous read mode during quad i/o ope ration, only eight clocks are needed. the instruction is ffh. to reset continuous read mod e during dual i/o operation, sixteen clocks are needed to shift in instruction ffffh.
W25Q20BW publication release date: november 22, 2013 - 39 - preliminary - revisio n c 8.2.21 page program (02h) the page program instruction allows from one byte t o 256 bytes (a page) of data to be programmed at previously erased (ffh) memory locations. a write e nable instruction must be executed before the device will accept the page program instruction (st atus register bit wel= 1). the instruction is initi ated by driving the /cs pin low then shifting the instruction code 02h fo llowed by a 24-bit address (a23-a0) and at least one data byte, into the di pin. the /cs pin must be held low for the entire length of the instruction while data is being sent to the device. the page program instruction sequence is shown in figure 19. if an entire 256 byte page is to be programmed, the last address byte (the 8 least significant address bits) should be set to 0. if the last address byte is not zero, and the number of clocks exceed the remainin g page length, the addressing will wrap to the beginn ing of the page. in some cases, less than 256 bytes (a partial page) can be programmed without having any effect on other bytes within the same page. one condition to perform a partial page program is that the number of clocks can not exceed the remaining page length. if more than 256 bytes are sent to the device the addressing will wrap to the beginning o f the page and overwrite previously sent data. as with the write and erase instructions, the /cs p in must be driven high after the eighth bit of the last byte has been latched. if this is not done the page program instruction will not be executed. after /c s is driven high, the self-timed page program instructio n will commence for a time duration of tpp (see ac characteristics). while the page program cycle is i n progress, the read status register instruction ma y still be accessed for checking the status of the bu sy bit. the busy bit is a 1 during the page program cycle and becomes a 0 when the cycle is finished an d the device is ready to accept other instructions again. after the page program cycle has finished th e write enable latch (wel) bit in the status regist er is cleared to 0. the page program instruction will not be executed if the addressed page is protected by the block protect (cmp, sec, tb, bp2, bp1, and bp0) bits. figure 19. page program instruction sequence diagra m
W25Q20BW - 40 - 8.2.22 quad input page program (32h) the quad page program instruction allows up to 256 bytes of data to be programmed at previously erased (ffh) memory locations using four pins: io 0 , io 1 , io 2 , and io 3 . the quad page program can improve performance for prom programmer and applica tions that have slow clock speeds <5mhz. systems with faster clock speed will not realize mu ch benefit for the quad page program instruction since the inherent page program time is much greate r than the time it take to clock-in the data. to use quad page program the quad enable in status register-2 must be set (qe=1). a write enable instruction must be executed before the device will accept the quad page program instruction (status register-1, wel=1). the instruction is initiated by driving the /cs pin low then shifting the instruction code 32h followed by a 24-bit address (a23-a0) an d at least one data byte, into the io pins. the /cs pin must be held low for the entire length of the instr uction while data is being sent to the device. all other functions of quad page program are identical to sta ndard page program. the quad page program instruction sequence is shown in figure 20. figure 20. quad input page program instruction sequ ence diagram
W25Q20BW publication release date: november 22, 2013 - 41 - preliminary - revisio n c 8.2.23 sector erase (20h) the sector erase instruction sets all memory within a specified sector (4k-bytes) to the erased state of all 1s (ffh). a write enable instruction must be execut ed before the device will accept the sector erase instruction (status register bit wel must equal 1). the instruction is initiated by driving the /cs pi n low and shifting the instruction code 20h followed a 24-bit sector address (a23-a0) (see figure 2). the sector erase instruction sequence is shown in figur e 21. the /cs pin must be driven high after the eighth bi t of the last byte has been latched. if this is not done the sector erase instruction will not be executed. after /cs is driven high, the self-timed sector era se instruction will commence for a time duration of t se (see ac characteristics). while the sector erase cycle is in progress, the read status register inst ruction may still be accessed for checking the stat us of the busy bit. the busy bit is a 1 during the sector erase cycle and becomes a 0 when the cycle is finished and the device is ready to accept other in structions again. after the sector erase cycle has finished the write enable latch (wel) bit in the st atus register is cleared to 0. the sector erase instruction will not be executed if the addressed p age is protected by the block protect (cmp, sec, tb , bp2, bp1, and bp0) bits (see status register memory protection table). figure 21. sector erase instruction sequence diagra m
W25Q20BW - 42 - 8.2.24 32kb block erase (52h) the block erase instruction sets all memory within a specified block (32k-bytes) to the erased state o f all 1s (ffh). a write enable instruction must be execut ed before the device will accept the block erase instruction (status register bit wel must equal 1). the instruction is initiated by driving the /cs pi n low and shifting the instruction code 52h followed a 24-bit block address (a23-a0) (see figure 2). the b lock erase instruction sequence is shown in figure 22. the /cs pin must be driven high after the eighth bi t of the last byte has been latched. if this is not done the block erase instruction will not be executed. a fter /cs is driven high, the self-timed block erase instruction will commence for a time duration of t be 1 (see ac characteristics). while the block erase cycle is in progress, the read status register inst ruction may still be accessed for checking the stat us of the busy bit. the busy bit is a 1 during the block erase cycle and becomes a 0 when the cycle is finished and the device is ready to accept other in structions again. after the block erase cycle has finished the write enable latch (wel) bit in the st atus register is cleared to 0. the block erase instruction will not be executed if the addressed p age is protected by the block protect (cmp, sec, tb , bp2, bp1, and bp0) bits (see status register memory protection table). figure 22. 32kb block erase instruction sequence di agram
W25Q20BW publication release date: november 22, 2013 - 43 - preliminary - revisio n c 8.2.25 64kb block erase (d8h) the block erase instruction sets all memory within a specified block (64k-bytes) to the erased state o f all 1s (ffh). a write enable instruction must be execut ed before the device will accept the block erase instruction (status register bit wel must equal 1). the instruction is initiated by driving the /cs pi n low and shifting the instruction code d8h followed a 24-bit block address (a23-a0) (see figure 2). the b lock erase instruction sequence is shown in figure 23. the /cs pin must be driven high after the eighth bi t of the last byte has been latched. if this is not done the block erase instruction will not be executed. a fter /cs is driven high, the self-timed block erase instruction will commence for a time duration of t be (see ac characteristics). while the block erase cy cle is in progress, the read status register instructio n may still be accessed for checking the status of the busy bit. the busy bit is a 1 during the block eras e cycle and becomes a 0 when the cycle is finished and the device is ready to accept other instruction s again. after the block erase cycle has finished t he write enable latch (wel) bit in the status register is cleared to 0. the block erase instruction will not be executed if the addressed page is protected by t he block protect (cmp, sec, tb, bp2, bp1, and bp0) bits (see status register memory protection table). figure 23. 64kb block erase instruction sequence di agram
W25Q20BW - 44 - 8.2.26 chip erase (c7h / 60h) the chip erase instruction sets all memory within t he device to the erased state of all 1s (ffh). a wr ite enable instruction must be executed before the devi ce will accept the chip erase instruction (status register bit wel must equal 1). the instruction is initiated by driving the /cs pin low and shifting t he instruction code c7h or 60h. the chip erase ins truction sequence is shown in figure 24. the /cs pin must be driven high after the eighth bi t has been latched. if this is not done the chip er ase instruction will not be executed. after /cs is driv en high, the self-timed chip erase instruction will commence for a time duration of t ce (see ac characteristics). while the chip erase cyc le is in progress, the read status register instruction may still be a ccessed to check the status of the busy bit. the busy bit is a 1 during the chip erase cycle and bec omes a 0 when finished and the device is ready to accept other instructions again. after the chip era se cycle has finished the write enable latch (wel) bit in the status register is cleared to 0. the chip er ase instruction will not be executed if any page is protected by the block protect (cmp, sec, tb, bp2, bp1, and bp0) bits (see status register memory protection table). figure 24. chip erase instruction sequence diagram
W25Q20BW publication release date: november 22, 2013 - 45 - preliminary - revisio n c 8.2.27 erase / program suspend (75h) the erase/program suspend instruction 75h, allows the system to interrupt a sector or block erase operation or a page program operation and then read from or program/erase data to, any other sectors o r blocks. the erase/program suspend instruction seque nce is shown in figure 25. the write status register instruction (01h) and era se instructions (20h, 52h, d8h, c7h, 60h, 44h) are not allowed during erase suspend. erase suspend is vali d only during the sector or block erase operation. if written during the chip erase operation, the erase suspend instruction is ignored. the write status register instruction (01h) and program instructions (02h, 32h, 42h) are not allowed during program suspend. program suspend is valid only during the p age program or quad page program operation. the erase/program suspend instruction 75h will be accepted by the device only if the sus bit in the status register equals to 0 and the busy bit equals to 1 while a sector or block erase or a page program operation is on-going. if the sus bit equal s to 1 or the busy bit equals to 0, the suspend instruction will be ignored by the device. a maximu m of time of t sus (see ac characteristics) is required to suspend the erase or program operation. the busy bit in the status register will be cleared from 1 to 0 within t sus and the sus bit in the status register will be se t from 0 to 1 immediately after erase/program suspend. for a previously resumed era se/program operation, it is also required that the suspend instruction 75h is not issued earlier tha n a minimum of time of t sus following the preceding resume instruction 7ah. unexpected power off during the erase/program suspe nd state will reset the device and release the suspend state. sus bit in the status register will also reset to 0. the data within the page, sector o r block that was being suspended may become corrupted. it i s recommended for the user to implement system design techniques against the accidental power inte rruption and preserve data integrity during erase/program suspend state. figure 25. erase/program suspend instruction sequen ce
W25Q20BW - 46 - 8.2.28 erase / program resume (7ah) the erase/program resume instruction 7ah must be written to resume the sector or block erase operation or the page program operation after an er ase/program suspend. the resume instruction 7ah will be accepted by the device only if the sus bit in the status register equals to 1 and the busy bit equals to 0. after issued the sus bit will be clear ed from 1 to 0 immediately, the busy bit will be se t from 0 to 1 within 200ns and the sector or block will co mplete the erase operation or the page will complet e the program operation. if the sus bit equals to 0 or th e busy bit equals to 1, the resume instruction 7ah will be ignored by the device. the erase/program re sume instruction sequence is shown in figure 26. resume instruction is ignored if the previous erase /program suspend operation was interrupted by unexpected power off. it is also required that a su bsequent erase/program suspend instruction not to b e issued within a minimum of time of t sus following a previous resume instruction. figure 26. erase/program resume instruction sequenc e
W25Q20BW publication release date: november 22, 2013 - 47 - preliminary - revisio n c 8.2.29 power-down (b9h) although the standby current during normal operatio n is relatively low, standby current can be further reduced with the power-down instruction. the lower power consumption makes the power-down instruction especially useful for battery powered a pplications (see icc1 and icc2 in ac characteristic s). the instruction is initiated by driving the /cs pin low and shifting the instruction code b9h as sho wn in figure 27. the /cs pin must be driven high after the eighth bi t has been latched. if this is not done the power-d own instruction will not be executed. after /cs is driv en high, the power-down state will entered within t he time duration of t dp (see ac characteristics). while in the power-down state only the release from power- down / device id instruction, which restores the de vice to normal operation, will be recognized. all o ther instructions are ignored. this includes the read st atus register instruction, which is always availabl e during normal operation. ignoring all but one instr uction makes the power down state a useful conditio n for securing maximum write protection. the device a lways powers-up in the normal operation with the standby current of icc1. figure 27. deep power-down instruction sequence dia gram
W25Q20BW - 48 - 8.2.30 release power-down / device id (abh) the release from power-down / device id instruction is a multi-purpose instruction. it can be used to release the device from the power-down state, or ob tain the devices electronic identification (id) num ber. to release the device from the power-down state, th e instruction is issued by driving the /cs pin low, shifting the instruction code abh and driving /cs high as shown in figure 28a. release from power-do wn will take the time duration of t res1 (see ac characteristics) before the device will re sume normal operation and other instructions are accepted. the /cs pin must remain high during the t res1 time duration. when used only to obtain the device id while not in the power-down state, the instruction is initiated by driving the /cs pin low and shifting the instructio n code abh followed by 3-dummy bytes. the device id bits are then shifted out on the falling edge of cl k with most significant bit (msb) first as shown in figure 28a. the device id values for the W25Q20BW is liste d in manufacturer and device identification table. the device id can be read continuously. the instruc tion is completed by driving /cs high. when used to release the device from the power-down state and obtain the device id, the instruction is the same as previously described, and shown in figu re 28b, except that after /cs is driven high it mus t remain high for a time duration of t res2 (see ac characteristics). after this time duration the device will resume normal operation and other instructions will be accepted. if the release from power-down / device id instruction is issued while an erase, pro gram or write cycle is in process (when busy equals 1) the instruction is ignored and will not have any effects on the current cycle. figure 28a. release power-down instruction sequence
W25Q20BW publication release date: november 22, 2013 - 49 - preliminary - revisio n c figure 28b. release power-down / device id instruct ion sequence diagram
W25Q20BW - 50 - 8.2.31 read manufacturer / device id (90h) the read manufacturer/device id instruction is an a lternative to the release from power-down / device id instruction that provides both the jedec assigne d manufacturer id and the specific device id. the read manufacturer/device id instruction is very similar to the release from power-down / device id instruction. the instruction is initiated by drivin g the /cs pin low and shifting the instruction code 90h followed by a 24-bit address (a23-a0) of 000000h. a fter which, the manufacturer id for winbond (efh) and the device id are shifted out on the falling ed ge of clk with most significant bit (msb) first as shown in figure 29. the device id values for the W25Q20BW is listed in manufacturer and device identificatio n table. the manufacturer and device ids can be read continuously, alternating from one to the other. th e instruction is completed by driving /cs high. figure 29. read manufacturer / device id diagram
W25Q20BW publication release date: november 22, 2013 - 51 - preliminary - revisio n c 8.2.32 read manufacturer / device id dual i/o (92h) the manufacturer / device id dual i/o instruction i s an alternative to the read manufacturer/device id instruction that provides both the jedec assigned m anufacturer id and the specific device id at 2x speed. the read manufacturer / device id dual i/o instruct ion is similar to the fast read dual i/o instructio n. the instruction is initiated by driving the /cs pin low and shifting the instruction code 92h follow ed by a 24-bit address (a23-a0) of 000000h, 8-bit continuou s read mode bits, with the capability to input the address bits two bits per clock. after which, the m anufacturer id for winbond (efh) and the device id are shifted out 2 bits per clock on the falling edg e of clk with most significant bits (msb) first as shown in figure 30. the device id values for the W25Q20BW is listed in manufacturer and device identification table.the manufacturer and device ids can be read c ontinuously, alternating from one to the other. the instruction is completed by driving /cs high. figure 30. read manufacturer / device id dual i/o d iagram note: the continuous read mode bits m7-0 must be set to fxh to be compatible with fast read dual i/o instr uction.
W25Q20BW - 52 - 8.2.33 read manufacturer / device id quad i/o (94h) the read manufacturer / device id quad i/o instruct ion is an alternative to the read manufacturer / device id instruction that provides both the jedec assigned manufacturer id and the specific device id at 4x speed. the read manufacturer / device id quad i/o instruct ion is similar to the fast read quad i/o instructio n. the instruction is initiated by driving the /cs pin low and shifting the instruction code 94h follow ed by a 24-bit address (a23-a0) of 000000h, 8-bit continuou s read mode bits and then four clock dummy cycles, with the capability to input the address bits four bits per clock. after which, the manufacturer id fo r winbond (efh) and the device id are shifted out fou r bits per clock on the falling edge of clk with mo st significant bit (msb) first as shown in figure 31. the device id values for the W25Q20BW is listed in manufacturer and device identification table. the m anufacturer and device ids can be read continuously , alternating from one to the other. the instruction is completed by driving /cs high. figure 31. read manufacturer / device id quad i/o d iagram note: the continuous read mode bits m7-0 must be set to fxh to be compatible with fast read quad i/o instr uction.
W25Q20BW publication release date: november 22, 2013 - 53 - preliminary - revisio n c 24 25 26 27 28 29 30 31 32 33 34 35 36 3 7 38 39 40 41 42 43 44 101 102 103 do 63 62 61 60 59 2 1 0 * *=msb do 24 25 26 27 28 29 30 31 32 33 34 35 36 3 7 38 39 40 41 42 43 44 101 102 103 do 63 62 61 60 59 2 1 0 * *=msb do 8.2.34 read unique id number (4bh) the read unique id number instruction accesses a fa ctory-set read-only 64-bit number that is unique to each W25Q20BW device. the id number can be used in conjunction with user software methods to help prevent copying or cloning of a system. the read un ique id instruction is initiated by driving the /cs pin low and shifting the instruction code 4bh followe d by a four bytes of dummy clocks. after which, the 64- bit id is shifted out on the falling edge of clk as shown in figure 32. figure 32. read unique id number instruction sequen ce
W25Q20BW - 54 - 8.2.35 read jedec id (9fh) for compatibility reasons, the W25Q20BW provides se veral instructions to electronically determine the identity of the device. the read jedec id instructi on is compatible with the jedec standard for spi compatible serial memories that was adopted in 2003 . the instruction is initiated by driving the /cs p in low and shifting the instruction code 9fh. the je dec assigned manufacturer id byte for winbond (efh) and two device id bytes, memory type (id15-id8) and capacity (id7-id0) are then shifted out on the falling edge of clk with most significant bit (msb) first as shown in figure 33. for memory type and capacity values refer to manufacturer and device id entification table. figure 33. read jedec id instruction sequence
W25Q20BW publication release date: november 22, 2013 - 55 - preliminary - revisio n c 8.2.36 erase security registers (44h) the W25Q20BW offers four 256-byte security register s which can be erased and programmed individually. these registers may be used by the sy stem manufacturers to store security and other important information separately from the main memo ry array. the erase security register instruction is similar to the sector erase instruction. a write enable instruction must be executed before the device will accept the erase security register instruction (st atus register bit wel must equal 1). the instruction is initiated by driving the /cs pin low and shifting t he instruction code 44h followed by a 24-bit address (a23-a0) to erase one of the four security registe rs. address a23-16 a15-12 a11-8 a7-0 security register #0* 00h 0 0 0 0 0 0 0 0 dont car e security register #1 00h 0 0 0 1 0 0 0 0 dont care security register #2 00h 0 0 1 0 0 0 0 0 dont care security register #3 00h 0 0 1 1 0 0 0 0 dont care * please note that security register 0 is reserved by winbond for future use. it is recommended to use security registers 1- 3 before u sing register 0. the erase security register instruction sequence is shown in figure 34. the /cs pin must be driven hig h after the eighth bit of the last byte has been latc hed. if this is not done the instruction will not b e executed. after /cs is driven high, the self-timed erase secu rity register operation will commence for a time duration of t se (see ac characteristics). while the erase security register cycle is in progress, the read status register instruction may still be accessed f or checking the status of the busy bit. the busy bi t is a 1 during the erase cycle and becomes a 0 when the cycle is finished and the device is ready to accep t other instructions again. after the erase security register cycle has finished the write enable latch (wel) bit in the status register is cleared to 0. t he security register lock bits (lb3-0) in the statu s register-2 can be used to otp protect the security registers. once a lock bit is set to 1, the corresponding security register will be permanently locked, erase security register instruction to tha t register will be ignored (see 8.1.9 for detail desc riptions). figure 34. erase security registers instruction seq uence instruction (44h)
W25Q20BW - 56 - 8.2.37 program security registers (42h) the program security register instruction is simila r to the page program instruction. it allows from o ne byte to 256 bytes of security register data to be p rogrammed at previously erased (ffh) memory locatio ns. a write enable instruction must be executed before the device will accept the program security registe r instruction (status register bit wel= 1). the instr uction is initiated by driving the /cs pin low then shifting the instruction code 42h followed by a 24-bit add ress (a23-a0) and at least one data byte, into the di pin. the /cs pin must be held low for the entire length of the i nstruction while data is being sent to the device. address a23-16 a15-12 a11-8 a7-0 security register #0* 00h 0 0 0 0 0 0 0 0 byte addr ess security register #1 00h 0 0 0 1 0 0 0 0 byte addre ss security register #2 00h 0 0 1 0 0 0 0 0 byte addre ss security register #3 00h 0 0 1 1 0 0 0 0 byte addre ss * please note that security register 0 is reserved by winbond for future use. it is recommended to use security registers 1- 3 before u sing register 0. the program security register instruction sequence is shown in figure 35. the security register lock bits (lb3-0) in the status register-2 can be used t o otp protect the security registers. once a lock b it is set to 1, the corresponding security register will be permanently locked, program security register instruction to that register will be ignored (see 8 .1.9, 8.2.21 for detail descriptions). figure 35. program security registers instruction s equence instruction (42h)
W25Q20BW publication release date: november 22, 2013 - 57 - preliminary - revisio n c 8.2.38 read security registers (48h) the read security register instruction is similar t o the fast read instruction and allows one or more data bytes to be sequentially read from one of the four security registers. the instruction is initiated by driving the /cs pin low and then shifting the instruction c ode 48h followed by a 24-bit address (a23-a0) an d eight dummy clocks into the di pin. the code and address bits are latched on the rising edge of the clk pin. after the address is received, the data byte o f the addressed memory location will be shifted out on the do pin at the falling edge of clk with most sig nificant bit (msb) first. the byte address is automatically incremented to the next byte address after each byte of data is shifted out. once the by te address reaches the last byte of the register (byte ffh), it will reset to 00h, the first byte of the register, and continue to increment. the instruction is compl eted by driving /cs high. the read security registe r instruction sequence is shown in figure 36. if a re ad security register instruction is issued while an erase, program or write cycle is in process (busy=1 ) the instruction is ignored and will not have any effects on the current cycle. the read security reg ister instruction allows clock rates from d.c. to a maximum of f r (see ac electrical characteristics). address a23-16 a15-12 a11-8 a7-0 security register #0* 00h 0 0 0 0 0 0 0 0 byte addr ess security register #1 00h 0 0 0 1 0 0 0 0 byte addre ss security register #2 00h 0 0 1 0 0 0 0 0 byte addre ss security register #3 00h 0 0 1 1 0 0 0 0 byte addre ss * please note that security register 0 is reserved by winbond for future use. it is recommended to use security registers 1- 3 before u sing register 0. figure 36. read security registers instruction sequ ence instruction (48h) instruction (48h)
W25Q20BW - 58 - 9. electrical characteristics (1) 9.1 absolute maximum ratings (2) parameters symbol conditions range unit supply voltage vcc C0.6 to vcc+0.4 v voltage applied to any pin v io relative to ground C0.6 to vcc+0.4 v transient voltage on any pin v iot <20ns transient relative to ground C2.0v to vcc+2.0v v storage temperature t stg C65 to +150 c lead temperature t lead see note (3) c electrostatic discharge voltage v esd human body model (4) C2000 to +2000 v notes: 1. specification for W25Q20BW is preliminary. see p reliminary designation at the end of this document. 2. this device has been designed and tested for the specified operation ranges. proper operation outsi de of these levels is not guaranteed. exposure to abso lute maximum ratings may affect device reliability. exposure beyond absolute maximum ratings may cause permanent damage. 3. compliant with jedec standard j-std-20c for smal l body sn-pb or pb-free (green) assembly and the european directive on restrictions on hazardous sub stances (rohs) 2002/95/eu. 4. jedec std jesd22-a114a (c1=100pf, r1=1500 ohms, r2=500 ohms). 9.2 operating ranges parameter symbol conditions spec unit min max supply voltage (1) vcc f r = 80mhz f r = 50mhz (read data 03h) 1.65 1.95 v ambient temperature, operating t a industrial C40 +85 c note: 1. vcc voltage during read can operate across the m in and max range but should not exceed 10% of the programming (erase/write) voltage.
W25Q20BW publication release date: november 22, 2013 - 59 - preliminary - revisio n c 9.3 power-up timing and write inhibit threshold parameter symbol spec unit min max vcc (min) to /cs low t vsl (1) 10 s time delay before write instruction t puw (1) 1 10 ms write inhibit threshold voltage v wi (1) 1.0 1.4 v note: 1. these parameters are characterized only. figure 37. power-up timing and voltage levels
W25Q20BW - 60 - 9.4 dc electrical characteristics parameter symbol conditions spec unit min typ max input capacitance c in (1) v in = 0v (1) 6 pf output capacitance cout (1) v out = 0v (1) 8 pf input leakage i li 2 a i/o leakage i lo 2 a standby current i cc 1 /cs = vcc, vin = gnd or vcc 25 50 a power-down current i cc 2 /cs = vcc, vin = gnd or vcc 1 5 a current read data / dual /quad 1mhz i cc 3 (2) c = 0.1 vcc / 0.9 vcc do = open 4/5/6 6/10/12 ma current read data / dual /quad 33mhz i cc 3 (2) c = 0.1 vcc / 0.9 vcc do = open 6/8/9 9/12/15 ma current read data / dual output read/quad output read 80mhz i cc 3 (2) c = 0.1 vcc / 0.9 vcc do = open 10/10/12 15/20/24 ma current write status register i cc 4 /cs = vcc 8 12 ma current page program i cc 5 /cs = vcc 20 25 ma current sector/block erase i cc 6 /cs = vcc 20 25 ma current chip erase i cc 7 /cs = vcc 20 25 ma input low voltage v il C0.5 vcc x 0.3 v input high voltage v ih vcc x 0.7 vcc + 0.4 v output low voltage v ol i ol = 100 a 0.2 v output high voltage v oh i oh = C100 a vcc C 0.2 v notes: 1. tested on sample basis and specified through des ign and characterization data. ta = 25 c, vcc = 1. 8v. 2. checker board pattern.
W25Q20BW publication release date: november 22, 2013 - 61 - preliminary - revisio n c 9.5 ac measurement conditions parameter symbol spec unit min max load capacitance c l 30 pf input rise and fall times t r , t f 5 ns input pulse voltages v in 0.2 vcc to 0.8 vcc v input timing reference voltages in 0.3 vcc to 0.7 vcc v output timing reference voltages o ut 0.5 vcc to 0.5 vcc v note: 1. output hi-z is defined as the point where data o ut is no longer driven. figure 38. ac measurement i/o waveform
W25Q20BW - 62 - 9.6 ac electrical characteristics description symbol alt spec unit min typ max clock frequency for all instructions except for read data (03h) f r f c d.c. 80 mhz clock frequency for read data instruction (03h) f r d.c. 50 mhz clock high, low time for all instructions except read data (03h) t clh 1 , t cll 1 (1) 6 ns clock high, low time for read data (03h) instruction t crlh , t crll (1) 8 ns clock rise time peak to peak t clch (2) 0.1 v/ns clock fall time peak to peak t chcl (2) 0.1 v/ns /cs active setup time relative to clk t slch t css 5 ns /cs not active hold time relative to clk t chsl 5 ns data in setup time t dvch t dsu 2 ns data in hold time t chdx t dh 5 ns /cs active hold time relative to clk t chsh 5 ns /cs not active setup time relative to clk t shch 5 ns /cs deselect time (for array read array read) t shsl 1 t csh 10 ns /cs deselect time (for erase or program read status registers and volatile status register write ) t shsl 2 t csh 50 ns output disable time t shqz (2) t dis 7 ns clock low to output valid t clqv 1 t v 1 7 ns clock low to output valid (for read id instructions ) t clqv 2 t v 2 7.5 ns output hold time t clqx t ho 0 ns /hold active setup time relative to clk t hlch 5 ns continued C next page
W25Q20BW publication release date: november 22, 2013 - 63 - preliminary - revisio n c 9.7 ac electrical characteristics ( contd) description symbol alt spec unit min typ max /hold active hold time relative to clk t chhh 5 ns /hold not active setup time relative to clk t hhch 5 ns /hold not active hold time relative to clk t chhl 5 ns /hold to output low-z t hhqx (2) t lz 7 ns /hold to output high-z t hlqz (2) t hz 12 ns write protect setup time before /cs low t whsl (3) 20 ns write protect hold time after /cs high t shwl (3) 100 ns /cs high to power-down mode t dp (2) 3 s /cs high to standby mode without electronic signature read t res 1 (2) 30 s /cs high to standby mode with electronic signature read t res 2 (2) 30 s /cs high to next instruction after suspend t sus (2) 20 s write status register time t w 10 15 ms byte program time (first byte) (4) t bp1 20 50 s additional byte program time (after first byte) (4) t bp2 2.5 10 s page program time t pp 0.4 0.8 ms sector erase time (4kb) t se 30 200/400 (5) ms block erase time (32kb) t be 1 120 800 ms block erase time (64kb) t be 2 150 1,000 ms chip erase time t ce 1 4 s notes: 1. clock high + clock low must be less than or equa l to 1/f c . 2. value guaranteed by design and/or characterizati on, not 100% tested in production. 3. only applicable as a constraint for a write stat us register instruction when srp0 bit is set to 1. 4. for multiple bytes after first byte within a pag e, t bpn = t bp1 + t bp2 * n (typical) and t bpn = t bp1 + t bp2 * n (max), where n = number of bytes programmed. 5. max value t se with <50k cycles is 200ms and >50k & <100k cycles is 400ms.
W25Q20BW - 64 - 9.8 serial output timing 9.9 serial input timing 9.10 hold timing
W25Q20BW publication release date: november 22, 2013 - 65 - preliminary - revisio n c 10. package specification 10.1 8-pin soic 150-mil (package code sn) l c d a1 a e b seating plane y 0.25 gauge plane e h e 4 1 5 8 l c d a1 a e b b b seating plane y 0.25 gauge plane e h e e h e 4 1 5 8 symbol millimeters inches min max min max a 1.35 1.75 0.053 0.069 a1 0.10 0.25 0.004 0.010 b 0.33 0.51 0.013 0.020 c 0.19 0.25 0.008 0.010 e (3) 3.80 4.00 0.150 0.157 d (3) 4.80 5.00 0.188 0.196 e (2) 1.27 bsc 0.050 bsc h e 5.80 6.20 0.228 0.244 y (4) --- 0.10 --- 0.004 l 0.40 1.27 0.016 0.050 0 10 0 10 notes: 1. controlling dimensions: millimeters, unless othe rwise specified. 2. bsc = basic lead spacing between centers. 3. dimensions d and e do not include mold flash pro trusions and should be measured from the bottom of the package. 4. formed leads coplanarity with respect to seating plane shall be within 0.004 inches.
W25Q20BW - 66 - 10.2 8-pin vsop8 150-mil (package code sv) symbol millimeter inches min typ. max min typ. max a 0.90 0.035 a1 0.01 0.05 0.0004 0.002 a2 0.8 0.031 q 0.19 0.20 0.21 0.007 0.008 0.008 b 0.33 0.51 0.33 0.020 c 0.125 bsc 0.005 bsc d 4.80 4.90 5.00 0.189 0.193 0.197 e 5.80 6.00 6.20 0.228 0.236 0.244 e1 3.80 3.90 4.00 0.150 0.154 0.157 e 1.27bsc 0.050 bsc l 0.40 0.71 1.27 0.016 0.028 0.050 0 10 0 10 notes: 1. dimension d does not include mold flash, protr usions or gate burrs. mold flash, protrusions and g ate burrs shall not exceed 0.018 inches [0.15mm] per side. 2. dimension e1 does not include interlead flash, interlead flash shall not exceed 0.010 inches [0.2 5mm] per side.
W25Q20BW publication release date: november 22, 2013 - 67 - preliminary - revisio n c 10.3 8-pad wson 6x5-mm (package code zp) symbol millimeters inches min nom max min nom max a 0.70 0.75 0.80 0.028 0.030 0.031 a1 0.00 0.02 0.05 0.000 0.001 0.002 b 0.35 0.40 0.48 0.014 0.016 0.019 c --- 0.20 ref. --- --- 0.008 ref. --- d 5.90 6.00 6.10 0.232 0.236 0.240 d2 3.35 3.40 3.45 0.132 0.134 0.136 e 4.90 5.00 5.10 0.193 0.197 0.201 e2 4.25 4.30 4.35 0.167 0.169 0.171 e (2) 1.27 bsc. 0.050 bsc. l 0.55 0.60 0.65 0.022 0.024 0.026 y 0.00 --- 0.075 0.000 --- 0.003
W25Q20BW - 68 - 8-pad wson 6x5-mm contd. symbol millimeters inches min nom max min nom max solder pattern m 3.40 0.134 n 4.30 0.169 p 6.00 0.236 q 0.50 0.020 r 0.75 0.026 notes: 1. advanced packaging information; please contact w inbond for the latest minimum and maximum specifica tions. 2. bsc = basic lead spacing between centers. 3. dimensions d and e do not include mold flash pro trusions and should be measured from the bottom of the package. 4. the metal pad area on the bottom center of the p ackage is connected to the device ground (gnd pin). avoid placement of exposed pcb vias under the pad.
W25Q20BW publication release date: november 22, 2013 - 69 - preliminary - revisio n c 10.4 8-pad uson 2x3-mm (package code ux) note: exposed pad dimension d 2 & e2 may be different by die size. symbol millimeter inches min typ. max min typ. max a 0.50 0.55 0.60 0.020 0.022 0.024 a1 0.00 0.02 0.05 0.000 0.001 0.002 b 0.20 0.25 0.300 0.008 0.010 0.012 c D 0.15 ref D D 0.006 D d 1.90 2.00 2.10 0.075 0.079 0.083 d2 1.55 1.60 1.65 0.061 0.063 0.065 e 2.90 3.00 3.10 0.114 0.118 0.122 e2 0.15 0.20 0.25 0.006 0.008 0.010 e D 0.50 D D 0.020 D l 0.40 0.45 0.50 0.016 0.018 0.020 l1 D 0.10 D D 0.004 D l3 0.30 0.35 0.40 0.012 0.014 0.016 y 0.000 D 0.075 0.000 D 0.003
W25Q20BW - 70 - 11. ordering information notes: 1. the w prefix is not included on the part marki ng. 2. only the 2 nd letter is used for the part marking. wson package type zp is not used for the part marki ng. uson package type ux has special top marking due to size limitation. 3. standard bulk shipments are in tube (shape e). p lease specify alternate packing method, such as tap e and reel (shape t) or tray (shape s), when placing orde rs. 4. for shipments with otp feature enabled, please c ontact winbond. w (1) 25q 2 0b w xx (2) w = winbond 25q = spiflash serial flash memory with 4kb secto rs, dual/quad i/o 20b = 2m-bit w = 1.65v to 1.95v sn = 8-pin soic 150-mil sv = 8-pin vsop 150-mil ux = 8-pad uson 2x3-mm zp = 8-pad wson 6x5-mm i = industrial (-40c to +85c) ( 3,4 ) g = green package (lead-free, rohs compliant, halog en-free (tbba), antimony-oxide-free sb 2 o 3 )
W25Q20BW publication release date: november 22, 2013 - 71 - preliminary - revisio n c 11.1 valid part numbers and top side marking the following table provides the valid part numbers for the W25Q20BW spiflash memory. please contact winbond for specific availability by density and pa ckage type. winbond spiflash memories use an 12-dig it product number for ordering. however, due to limite d space, the top side marking on all packages use an abbreviated 10-digit number. package type density product number top side marking sn soic - 8 150mil 2m-bit W25Q20BWsnig 25q20bwnig sv v so p - 8 150mil 2m-bit W25Q20BWsvig 25q20bwvig zp (1) wson-8 6x5mm 2m-bit W25Q20BWzpig 25q20bwig ux (2) uson-8 2x3mm 2m-bit W25Q20BWuxig 2eyww 0gxxxx note: 1. wson package type zp is not used in the top side marking. 2. uson package type ux has special top marking due to size limitation. 2e = W25Q20BW; y = year ; xxxx: lot id 3. for shipments with otp feature enabled, please contact winbond.
W25Q20BW - 72 - 12. revision history version date page description a 08/06/10 new create preliminary b 12/02/10 5-6, 67-69 added uson package c 11/22/13 5-7,.67-60 50-52 58 71 70-71 added vsop package updated description of 90h/92h/94h updated vcc rating added uson 2x3 top side marking updated otp function, please contact winbond preliminary designation the preliminary designation on a winbond datasheet indicates that the product is not fully characterized. the specifications are subject to change and are no t guaranteed. winbond or an authorized sales representative should be consulted for current info rmation before using this product. trademarks winbond and spiflash are trademarks of winbond electronics corporation . all other marks are the property of their respectiv e owner. important notice winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, at omic energy control instruments, airplane or spaces hip instruments, transportation instruments, traffic si gnal instruments, combustion control instruments, o r for other applications intended to support or sustain l ife. further more, winbond products are not intended for applications wherein failure of winbond products could result or lead to a situation where in personal injury, death or severe property or environmental d amage could occur. winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify winbond for any damages resulting from such improper use o r sales.

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